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(ｃ) 12bit
D.OUT1
D.OUT2
0±3ns
Previous Cycle
T
CLK
31.25ns (32MHz)
1.41V
1.075V
DA7-1 DA6-1 N.C DB7 DB6 DB11 DB10 DA7 DA6
DB3-1 DB2-1 N.C FVAL LVAL DB5 DB4 DB3 DB2
DA10-1 DA9-1 DB1 DB0 DB9 DB8 DA11 DA10 DA9
DA1-1 DA0-1 DA8 DA5 DA4 DA3 DA2 DA1 DA0
X3
X2
X1
X0
CLKX
Next Cycle
(
VD
)
(
HD
)
0±3ns
Previous Cycle
T
CLK
31.25ns (32MHz)
1.41V
1.075V
DD7-1 DD6-1 N.C DD11 DD10 DC7 DC6 DD7 DD6
DC11-1 DC10-1 N.C FVAL LVAL DD9 DD8 DC11 DC10
DC2-1 DC1-1 DC9 DC8 DC5 DC4 DC3 DC2 DC1
DD1-1 DD0-1 DC0 DD5 DD4 DD3 DD2 DD1 DD0
Y3
Y2
Y1
Y0
CLKY
Next Cycle
(
VD
)
(
HD
)