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Camera Bus Timings
The non-decode engine outputs pixel data via an 8-bit parallel data bus. The rate at which data is output is
determined by the pixel clock, which can be set for 48, 24, or 12 MHz. When the horizontal and vertical synch
signals are high, valid pixel data is latched on the rising edge of the PCLK. New pixel data is then driven on to
the bus on the falling edge. The VSYNC, HSYNC, and Pixel Data timings are relative to the PCLK and are
related as shown in the following timing diagram.
Figure 12. Parallel Data Output Video Timing*
Parallel Data Interface Timings*
Symbol Description Min. Max. Unit
f
PCLK
PCLK frequency 48 MHz
t
PCLKL
PCLK low width [1/2*1/fPCLK)] – 0.5 [1/2*1/fPCLK)] + 0.5 ns
t
PCLKH
PCLK high width [1/2*1/fPCLK)] – 0.5 [1/2*1/fPCLK)] + 0.5 ns
t
DV
PCLK to output valid -0.1 +2.5 ns
Table 1. Parallel Data Interface Timings*
* © of STMicroelectronics – All rights reserved.