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Page 7 of 8 Version 1.0 11/08/01
Performance Enhancements and Improvements:
v The CPC710 DD3.x revision has improvements to support PCI Long Burst Write operations
and improvements in the deadlock prevention circuits. These enhancements can be selected
by programming select bits in PCI local registers PCILx_PSWCR and PCILx_DLKCTRL.
Ø Crossing a 4K boundary during burst operations results in a stop on the PCI bus. By
default operation, snooping is done on the current PCI master’s address. A new option is
provided to allow for anticipation logic to snoop ahead to the next address. Set PCI local
register PCILx_PSWCR [17] to “1” to enable the snoop ahead logic.
Ø There have been several changes to the deadlock avoidance logic. The CPC710 DD2
errata #8 and #9, relating to defects in the deadlock circuitry, have been fixed in the
CPC710 DD3.x revision. In addition, there are three improvements that can be selected
by setting the appropriate bits.
§ PCILx_DLKCTRL [27] – when set to “0” enables the erratum #8 correction logic to
prevent potential deadlock in multiprocessor configurations when one CPU is
attempting a PCI read. For more details on the erratum, please read the CPC710
DD2 Errata List. Setting this bit to “1” disables the correction logic.
§ PCILx_DLKCTRL [28] – when set to “0” enables the erratum #9 correction logic to
function correctly when the programmed value in the PCI local register
PCILx_DLKCTRL [8:15] is greater than 0x0F. Setting this bit to a “1” disables the
correction logic.
§ PCILx_DLKCTRL [29] - when set to “1” results in the following: When a read is
already in progress to an address defined in the deadlock avoidance address range,
an ARTRY will be generated for all accesses except the access to the main memory
for that read. Setting this bit to a “0” disables this logic. The default state for this bit is
recommended, as other methods of deadlock avoidance have proven to be flexible
enough to resolve problems without use of this logic.
§ PCILx_DLKCTRL [30] - when set to “0” results in the following: The processor ID is
taken into account in the deadlock avoidance logic. Setting this bit to a “1” causes the
deadlock logic to ignore the processor ID.
§ PCILx_DLKCTRL [31] - when set to “0” results in the following: The deadlock
avoidance logic using the signals MEMREQ/MEMACK and DLK/NODLK are masked.
Setting this bit to a “1” causes the deadlock logic to generate these signals as usual.
Please send questions or comments about this document to Embedded PowerPC
Technical Support: ppcsupp@us.ibm.com
IBM Corporation
PowerPC Embedded Processor Solutions
Applications Engineering
Research Triangle Park, NC 27709