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Appendix A. Connector pin assignments
IDE connectors
1
2
40
39
Figure 22 (Page 3 of 3). PCI connector pin assignments
Pin Signal I/O Pin Signal I/O
A45 Address/Data 14 I/O B45 Address/Data 14 I/O
A46 Ground NA B46 Ground NA
A47 Address/Data 12 I/O B47 Address/Data 12 I/O
A48 Address/Data 10 I/O B48 Address/Data 10 I/O
A49 Ground NA B49 Ground NA
A50 Key NA B50 Key NA
A51 Key NA B51 Key NA
A52 Address/Data 8 I/O B52 Address/Data 8 I/O
A53 Address/Data 7 I/O B53 Address/Data 7 I/O
A54 +3.3 V DC NA B54 +3.3 V DC NA
A55 Address/Data 5 I/O B55 Address/Data 5 I/O
A56 Address/Data 3 I/O B56 Address/Data 3 I/O
A57 Ground NA B57 Ground NA
A58 Address/Data 1 I/O B58 Address/Data 1 I/O
A59 +5 V DC (I/O) NA B59 +5 V DC (I/O) NA
A60 ACK64# I/O B60 ACK64# I/O
A61 +5 V DC NA B61 +5 V DC NA
A62 +5 V DC NA B62 +5 V DC NA
Figure 23 (Page 1 of 2). IDE connector pin assignments
Pin Signal I/O Pin Signal I/O
1 RESET O 21 NC NA
2 Ground NA 22 Ground NA
3 Data bus bit 7 I/O 23 I/O write O
4 Data bus bit 8 I/O 24 NC NA
5 Data bus bit 6 I/O 25 I/O read O
6 Data bus bit 9 I/O 26 Ground NA
7 Data bus bit 5 I/O 27 I/O channel ready I
8 Data bus bit 10 I/O 28 ALE O
9 Data bus bit 4 I/O 29 NC NA
10 Data bus bit 11 I/O 30 Ground NA
11 Data bus bit 3 I/O 31 IRQ I
12 Data bus bit 12 I/O 32 CS16# I
13 Data bus bit 2 I/O 33 SA1 O
14 Data bus bit 13 I/O 34 PDIAG# I
Appendix A. Connector pin assignments 31