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8.3.1.2.1 SRAM Memory Array Space .............................................514
8.3.1.2.2 Memory-Mapped Register Space......................................514
8.3.1.2.3 North Internal Bus Port Address Decode ..........................514
8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) .....514
8.3.1.5.1 SRAM State Machine and Pipeline Queues......................514
8.3.1.5.2 Error Correction Logic .......................................................515