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Read 32-bit data and 7-bit ECC
Compute the syndrome by passing the 32-bit data through the G-Matrix and XORing the
7-bit result with the 7-bit ECC
if the syndrome <> 0 {ECC Error}
Look up in H-matrix to determine error type
Register the address where the error occurred
if error is correctable {single bit}
if single-bit error correction is enabled
Correct data
Send corrected data to internal bus
if single bit error reporting is enabled
Interrupt core for software scrubbing
else {uncorrectable}
if the read cycle is not part of a RMW cycle {read}
Target-Abort the Internal Bus read transaction.
else {write requiring RMW}
Merge the new data portion with the read data from memory
Generate the new ECC with the G-matrix
Write new data and ECC
if multi-bit error reporting is enabled
Interrupt the core for uncorrectable error