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31:8 00 0000h Reserved
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2
FIFO Error Status (FIFOE): In non-FIFO mode, this bit is clear (0). In FIFO Mode,
this bit is set (1) when there is at least one parity error, framing error, or break
indication for any of the characters in the FIFO. A processor read to the Line Status
register does not reset this bit. FIFOE is reset when all error bytes have been read
from the FIFO. FIFOE being set to 1 does NOT generate an interrupt.
0 = No errors exit in the receive FIFO
1 = At least one character in receiver FIFO has errors
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Transmitter Empty (TEMT): Set (1) when the Transmit Holding register and the
Transmitter Shift register are both empty. It is reset to zero (0) when either the
Transmit Holding register or the Transmitter Shift register contains a data character.
In FIFO mode, TEMT is set to 1 when the transmitter FIFO and the Transmit Shift
register are both empty.
0 = There is data in the Transmit Shift register, the Transmit Holding register, or the
FIFO
1 = All the data in the transmitter has been shifted out