Filter
Top Products
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 113
Host Software Interface
Flow control is set by three configuration bits: one for transmit and two for receive flow control.
The default setting is off (Section 6.4.2.3, “Configure (010b)”). Software can interrogate the N-
Way registers to determine whether to turn it on. Flow control cannot be activated by auto-
negotiation alone.
The 8255x (except the 82557) provides status information to software regarding flow control. If the
device is currently paused from sending frames or if it is sending a pause frame, it sets an
indication in the flow control register. The device also has statistical counters that count the number
of pause requests sent and received (Section 6.3.2.4, “Statistical Counters”).
6.6.2.3.1 Transmit Flow Control
In FC mode, the controller receives FC frames independently of the state of the receive FIFO. This
allows other stations to put pressure on the device. The received FC frame is passed to the FIFO
only if it is configured for this (according to the reject FC bit, Section 6.4.2.3, “Configure (010b)”)
and only if there is room for it. The reject FC bit causes the device to reject frames sent to the
special FC multicast address. However, if the FC frame was destined to the device individual
address, the frame is passed to the FIFO regardless of the reject FC bit.
After a pause request is received, a 16 bit count down register is loaded with the time parameter
value that was in the pause frame. The counter decrements each slot time and stops when it reaches
zero. Upon receiving another pause frame, the device reloads the counter with the new time
parameter.
If the value of the counter is not zero, transmission of future frames is inhibited. This does not
interfere with the current transmission. The currently transmitted frame is completed and further
transmits are paused. This does not prevent the device from transmitting FC frames itself if it is
required to.
6.6.2.3.2 Receive Flow Control
In FC mode, the controller detects potential overrun conditions and sends a pause frame to the
other node. The transmission of the pause frame occurs after the current transmit is completed
(there is no immediate termination of transmissions).
The time parameter for the pause frame assembly is based on a pre-configured value that comes
from the configure command.
The prediction of overruns occurs through detection of a threshold crossing in the receive FIFO, as
defined in Section 6.3.8, “Flow Control Register”. When the receive FIFO is filled beyond
threshold value, a pause command is sent (with the pre-configured time value). Once a predicted
overrun is detected, the device remains in the congested state until the receive FIFO is absolutely
empty (no bytes in the receive FIFO).
The device has two additional configurable modes that affect transmit flow control. These modes
are “ReStop” and “ReStart” and are detailed below:
• ReStop. The controller has sent a pause command. Just before pause time (sent by the device)
expires, if the receive FIFO is not empty, the device sends another pause command. The
additional pause is sent so that it is assured to reach the congester before the pause time
expires.
• ReStart. The controller has sent a pause command. When the receive FIFO is empty, an XON
(PAUSE(0)) command is sent. The same mechanism used for sending pause commands is used
for sending pause (time equals 0) commands. In this mode, the device sends a pause command
and waits for the receive FIFO to empty. When it is empty, the device sends an XON command