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Map and Paging Control Register
EPM-4 Reference Manual Reference – 41
Map and Paging Control Register
MPCR (READ/WRITE) 00E3H
D7 D6 D5 D4 D3 D2 D1 D0
FPGEN Reserved Reserved Reserved Reserved PG2 PG1 PG0
Table 11: Map and Paging Control Register Bit Assignments
Bit Mnemonic Description
D7 FPGEN FLASH Paging Enable — Enables a 64KB page frame from E0000h to
EFFFFh. Used to gain access to the on-board FLASH memory.
FPGEN = 0 FLASH page frame disabled.
FPGEN = 1 FLASH page frame enabled.
Note: When FPGEN = 1, the Page Select bits are used to access various blocks within
the FLASH. The "D0000h 64k page function" in CMOS Setup must be set to "ISA Bus".
D6-D3 — Reserved — These bits have no function.
D2-D0 PG2-PG0 Page Select — Selects which 64K block of FLASH will be mapped into the page
frame.
Memory Range within
PG2 PG1 PG0 FLASH
0 0 0 000000h to 00FFFFh
0 0 1 010000h to 01FFFFh
0 1 0 020000h to 02FFFFh
0 1 1 030000h to 03FFFFh
1 0 0 040000h to 04FFFFh
1 0 1 050000h to 05FFFFh
1 1 0 060000h to 06FFFFh
1 1 1 070000h to 07FFFFh
.