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AT INTERFACE DESCRIPTION
5 – 4
DMA Timing
SRETEMARAPGNIMIT0EDOM1EDOM2EDOM
0t)nim(emiTelcyCsn084sn051sn021
CtyaledQRAMDotKCAMD
Dt)nim(-WOID/-ROIDsn512sn08sn07
Et)nim(sseccaatad-ROIDsn051sn06
Ft)nim(dlohatad-ROIDsn5sn5sn5
Gt)nim(putesatad-WOID/-ROIDsn001sn03sn02
Ht)nim(dlohatad-WOIDsn02sn51sn01
It)nim(putes-WOID/-ROIDotKCAMD 000
Jt)nim(dlohKCAMDot-WOID/-ROIDsn02sn5sn5
rKt)nim(htdiweslupdetagen-ROIDsn05sn05sn52
wKt)nim(htdiweslupdetagen-WOIDsn512sn05sn52
rLt)xam(yaledQRAMDot-ROIDsn021sn04sn53
wLt)xam(yaledQRAMDot-WOIDsn04sn04sn53
Zt)xam(etatsirtot-KCAMDsn02sn52sn52
Figure 5 - 3
Multi-word DMA Data Transfer