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NI 6115/6120 User Manual I-2 ni.com
AOGND signal
analog output signal connections, 4-14
description (table), 4-3
avoiding false triggering (note), 3-6
B
base address for NI 6115/6120 device, B-2
below-low-level analog triggering mode, 3-6
bipolar input, 3-3
block diagrams
analog trigger, 3-6
NI 6115 block diagram, 3-1
NI 6120 block diagram, 3-2
phase-locked loop circuit (figure), 3-10
bus
CompactPCI
master device slot support (note), 2-2
using PXI with CompactPCI, 1-2
interface specifications, A-17
PCI
overview, 1-1
PCI Local Bus Specification, 1-1, 2-3
PXI, 1-1
master device slot support (note), 2-2
NI PXI-6115/6120 J2 pin
assignments (table), 1-3
PXI Specification Revision 2.0,
1-2, 2-3
RTSI
device and RTSI clocks, 3-12
overview, 1-1
PCI RTSI Bus Signal Connection
(figure), 3-13
RTSI triggers, 3-12
timing signal routing, 3-10
using PXI with CompactPCI, 1-2
C
cables
See also I/O connectors
custom cabling, 1-6
field wiring considerations, 4-39
optional equipment, 1-6
calibration
external calibration, 5-2
loading calibration constants, 5-1
self-calibration, 5-2
calibration certificate, C-2
clocks
correlating DIO signals, 4-16
device and RTSI clocks, 3-12
commonly asked questions. See questions and
answers
common-mode signal rejection, 4-12
CompactPCI, using with PXI, 1-2
configuration
description, 2-3
questions about, B-2
connectors. See I/O connectors
contacting National Instruments, C-2
conventions used in manual, xi
CONVERT* signal
See also PFI2/CONVERT* signal
input timing (figure), 4-26
output timing (figure), 4-26
RTSI bus signal connections
(figure), 3-13
timing connections, 4-26
typical posttriggered acquisition
(figure), 4-21
typical pretriggered acquisition
(figure), 4-21
correlated digital I/O. See digital I/O
counter/timer applications, B-5
custom cabling, 1-6
customer
education, C-1