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CHAPTER 22 INTERRUPT FUNCTIONS
7
IEPSW
6
Z
5
RBS1
4
AC
3
RBS0
2
0
1
ISP
0
CY
02H
After
Reset
ISP
0
Used when Normal Instruction is Executed
Priority of Interrupt Currently Being Received
High-priority interrupt servicing
(low-priority interrupt disable)
1
Interrupt request not acknowledged or low-priority
interrupt servicing
(all-maskable interrupts enable)
IE Interrupt Request Acknowledge Enable/Disable
0 Disable
1 Enable
(6) Program status word (PSW)
The program status word is a register to hold the instruction execution result and the current status for
interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple
interrupt servicing are mapped.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and
dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, and when the BRK
instruction is executed, the contents of PSW automatically is saved into a stack and the IE flag is reset to
0. If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged
interrupt are transferred to the ISP flag. The acknowledged contents of PSW is also saved into the stack
with the PUSH PSW instruction. It is reset from the stack with the RETI, RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 22-9. Program Status Word Format