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CHAPTER 24 STANDBY FUNCTION
24.2 Standby Function Operations
24.2.1 HALT mode
(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock. The operating status in the HALT mode is described below.
Table 24-1. HALT Mode Operating Status
HALT mode setting HALT execution during HALT execution during
main system clock operation subsystem clock operation
w/ subsystem w/o. subsystem Main system Main system
Item clock
Note 1
clock
Note 2
clock oscillates clock stops
Clock Generator Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops.
CPU Operation stops.
Port (output latch) Status before HALT mode setting is held.
16-bit timer/event counter Operable. Operable when watch timer output
is used as count clock (with fXT
selected as count clock of watch
timer).
8-bit timer/event counter 1 and 2
Operable. Operable when TI1 or TI2 is
selected as count clock.
8-bit timer/event counter 5 and 6
Operable. Operable when TI5 or TI6 is
selected as count clock.
Watch timer Operable when Operable. Operable when fXT is selected
fXX/2
7
is selected as count clock.
as count clock.
Watchdog timer Operable. Operation stops.
A/D converter Operable. Operation stops.
D/A converter Operable.
Real-time output port Operable.
Serial Interface
When a function other than Operable Operable at external SCK.
auto transmit/receive is used
When auto transmit/receive Operation stops.
function is used
External interrupt
INTP0 Operable when a clock (fXX/2
5
, fXX/2
6
, fXX/2
7
) for the Operation stops.
peripheral hardware is selected as sampling clock.
INTP1 to INTP6 Operable.
Bus lines in external expansion
AD0 to AD7 Enters high impedance state.
A0 to A15 Holds the state before HALT mode is set.
ASTB Outputs low level.
WR, RD Outputs high level.
WAIT Enters high impedance state.
Notes 1. Including case when external clock is supplied.
2. Including case when external clock is not supplied.