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CHAPTER 8 16-BIT TIMER/EVENT COUNTER
0 0 0 0 0 0 SCS1 SCS0
76543210Symbol
SCS
FF47H 00H R/W
Address After Reset R/W
SCS1 SCS0
00
01
10
11
INTP0 Sampling Clock Selection
MCS = 1 MCS = 0
f
XX
/2
N
f
X
/2
7
(39.1 kHz)f
XX
/2
7
f
X
/2
8
(19.5 kHz)
f
X
/2
5
(156.3 kHz)f
XX
/2
5
f
X
/2
6
(78.1 kHz)
f
X
/2
6
(78.1 kHz)f
XX
/2
6
f
X
/2
7
(39.1 kHz)
(7) Sampling clock select registers (SCS)
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is removed with sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS value to 00H.
Figure 8-9. Sampling Clock Select Register Format
Caution f
XX/2
N
is the clock supplied to the CPU, and fXX/2
5
, fXX/2
6
, and fXX/2
7
are clocks supplied to
peripheral hardware. fXX/2
N
is stopped in HALT mode.
Remarks 1. N : Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)
(N = 0 to 4)
2. f
XX : Main system clock frequency (fX or fX/2)
3. fX : Main system clock oscillation frequency
4. MCS : Bit 0 of oscillation mode selection register (OSMS)
5. Figures in parentheses apply to operation with f
X = 5.0 MHz.