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ELECTRICAL SPECIFICATION SSD-CXXX(I)-3600 DATA SHEET
SILICONSYSTEMS PROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
3600C-04DSR PAGE 20 FEBRUARY 2, 2009
True IDE Read/Write Access Timing
Figure 6: True IDE Read/Write Access Timing Diagram
Note: (1) IOIS16 and INPACK are not supported.
Table 16: True IDE Read/Write Access Timing
Symbol Parameter Minimum Maximum Units
t
ICL
Cycle Time 100 - ns
t
AVRWL
Address Valid to DIOR,DIOW Setup Time 15 - ns
t
RWPW
DIOR, DIOW Pulse Width 65 - ns
t
DVWL
DIOW Data Setup Time 20 - ns
t
DXWH
DIOW Data Hold Time 5 - ns
t
DVRL
DIOR Data Setup Time 15 - ns
t
DXRH
DIOR Data Hold Time 5 - ns
t
AV16L
Address Valid to IOCS16 Assertion - (1) ns
t
AX16H
Address Valid to IOCS16 Negation - (1) ns
t
AXRWH
DIOW,DIOR to Address Valid Hold Time 10 - ns
t
IOST
IORDY Setup Time - (1) ns
t
IOPW
IORDY Pulse Width - (1) ns
ADDRESS Valid
CS0, CS1, DA[2::0]
____ _____
DIOR,DIOW
WRI T E
DD[15::00]
READ
DD[15::00]
IORDY
tIC L
tDVW L
tAVRWL
tRWPW
tAXRWH
tA X16H
tDXW H
tDVRL
tIO S T
tIOP W
tDXRH
tAV16L
______
IOIS16