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BIOS Setup Utility SY-5SSM & SY-5SSM/5
49
CHIPSET FEATURES SETUP
CHIPSET
FEATURES
Setting Description Note
Ref/Act
Command Delay
6T
5T,7T, 8T
Set the DRAM clock of the
refresh command to
refresh/active command
delay.
Default
Refresh Queue
Depth
12
0, 4, 8,
Set the depth of refresh
queue.
Default
RAS Precharge
Time
3T
2T, 4T, 5T
The precharge time is the
number of cycles it takes for
the RAS to accumulate its
charge before DRAM
refreshes. If insufficient time
is allowed, refresh may be
incomplete and the DRAM
may fail to retain data.
Default
RAS to CAS
Delay
3T
2T,4T,5T
When DRAM is refreshed,
both rows and columns are
addressed separately. This
setup item allows you to
determine the timing of the
transition from RAS (row
address strobe) to CAS
(column address strobe).
Default
Disabled
CPU to PCI Burst
Mom. WR
Enabled
Select enabled permits PCI
burst memory write cycles,
for faster performance.
When disabled,
performance is slightly
slower, but more reliable.
Default
Disabled
CPU to PCI Post
Write
Enabled
Select enabled to use a fast
buffer for posting writes to
memory. Using a fast
buffer releases the CPU
before completion of a write
cycle to DRAM.
Default