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MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
®
Technology in a Small Footprint
Datasheet
SMSC LAN8710/LAN8710i 27 Revision 1.0 (04-15-09)
DATASHEET
comprised of 16 pins for data and control is defined. In devices incorporating many MACs or
transceiver interfaces such as switches, the number of pins can add significant cost as the port counts
increase. The management interface (MDIO/MDC) is identical to MII. The RMII interface has the
following characteristics:
It is capable of supporting 10Mb/s and 100Mb/s data rates
A single clock reference is used for both transmit and receive.
It provides independent 2 bit wide (di-bit) transmit and receive data paths
It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
The RMII includes 6 interface signals with one of the signals being optional:
transmit data - TXD[1:0]
transmit strobe - TXEN
receive data - RXD[1:0]
receive error - RXER (Optional)
carrier sense - CRS_DV
Reference Clock - (RMII references usually define this signal as REF_CLK)
4.6.2.1 CRS_DV - Carrier Sense/Receive Data Valid
The CRS_DV is asserted by the LAN8710/LAN8710i when the receive medium is non-idle. CRS_DV
is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode.
That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous
zeroes in 10 bits are detected, carrier is said to be detected.
Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which
presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble
boundaries). If the LAN8710/LAN8710i has additional bits to be presented on RXD[1:0] following the
initial deassertion of CRS_DV, then the LAN8710/LAN8710i shall assert CRS_DV on cycles of
REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of
REF_CLK which present the first di-bit of a nibble. The result is: Starting on nibble boundaries
CRS_DV toggles at 25 MHz in 100Mb/s mode and 2.5 MHz in 10Mb/s mode when CRS ends before
RXDV (i.e. the FIFO still has bits to transfer when the carrier event ends.) Therefore, the MAC can
accurately recover RXDV and CRS.
During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV
is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal
decoding takes place.
4.6.3 MII vs. RMII Configuration
The LAN8710/LAN8710i must be configured to support the MII or RMII bus for connectivity to the MAC.
This configuration is done through the RXD2/RMIISEL pin.
MII or RMII mode selection is configured based on the strapping of the RXD2/RMIISEL pin as
described in Section 5.3.9.3.
Most of the MII and RMII pins are multiplexed. Table 4.2, "MII/RMII Signal Mapping" describes the
relationship of the related device pins to the MII and RMII mode signal names.