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Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Revision 1.7 (10-02-08) 36 SMSC LAN9500/LAN9500i
DATASHEET
4.5.4 EEPROM Timing
The following specifies the EEPROM timing requirements for LAN9500/LAN9500i:
Figure 4.4 EEPROM Timing
Table 4.11 EEPROM Timing Values
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ckcyc
EECLK Cycle time 1110 1130 ns
t
ckh
EECLK High time 550 570 ns
t
ckl
EECLK Low time 550 570 ns
t
cshckh
EECS high before rising edge of EECLK 1070 ns
t
cklcsl
EECLK falling edge to EECS low 30 ns
t
dvckh
EEDO valid before rising edge of EECLK 550 ns
t
ckhdis
EEDO disable after rising edge EECLK 550 ns
t
dsckh
EEDI setup to rising edge of EECLK 90 ns
t
dhckh
EEDI hold after rising edge of EECLK 0 ns
t
ckldis
EECLK low to data disable (OUTPUT) 580 ns
t
cshdv
EEDIO valid after EECS high (VERIFY) 600 ns
t
dhcsl
EEDIO hold after EECS low (VERIFY) 0 ns
t
csl
EECS low 1070 ns
EECLK
EEDO
EEDI
EECS
t
ckldis
t
cshckh
EEDI (VERIFY)
t
ckh
t
ckl
t
ckcyc
t
cklcsl
t
csl
t
dvckh
t
ckhdis
t
dsckh
t
dhckh
t
dhcsl
t
cshdv