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CHAPTER
1
Watchdog Timer
The system management controller (SMC) on the Netra CP2500 implements a
watchdog service that captures catastrophic faults in the Solaris OS running on the
CPU board. The watchdog service reports such faults to the baseboard management
controller (BMC) by means of either an IPMI message or by a de-assertion of the
CPU’s HEALTHY# signal.
This chapter contains the following sections:
■ “Overview” on page 1
■ “PICL Plug-In Module” on page 2
■ “Watchdog Node Management Code” on page 5
■ “OpenBoot PROM Interface” on page 21
Overview
The Netra CP2500 SMC provides two watchdog timers: the watchdog level 2 (WD2)
timer and the watchdog level 1 (WD1) timer. Management applications (for example,
the Managed Object Hierarchy on the Netra CT 810/410 server or a third-party
application on a cPSB server) start the timers, and the Solaris OS periodically pats
the timers before they expire. If the WD2 timer expires, the watchdog function of the
WD2 timer forces the SPARC
®
processor to optionally reset. The maximum range for
WD2 is 255 seconds.
The WD1 timer is typically set to a shorter interval than the WD2 timer.
Management applications can examine the expiration status of the WD1 timer to get
advance warning if the main timer, WD2, is about to expire. The management
application has to start WD1 before it can start WD2. If WD1 expires, then WD2
starts only if enabled. The maximum range for WD1 is 6553.5 seconds.
The Solaris PICL module provides interfaces to the watchdog timer in SMC.