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ChronosGUI
frequencyshouldbeenteredhereinthisformat:xx.xxx(specifiedinMHz).
Step3.OutputCalculatorandApplyPLLSettings.
ThesecondrowofcalculationsisusedtoobtainthePLLsettingsnecessarytoachieveaparticular
outputfrequencyprovidedagiveninputfrequencytoCDCE421.Theinputmustbeenteredinthe
secondrowaswellasthelocationprovidedattheinputofthePLLblockdiagram.AftertheCalculate
buttonispressed,theadjacentdrop-downmenupopulateswithseveralchoicesforthegiveninput.
Thedesiredoutputcanthenbechosenfromthislist.Choosingoneoutputsetsthedividersettings
withinthePLL.ClickingApplynexttothedrop-downmenuresultsinwritingthePLLsettingstothe
SRAM.IfLVPECLoutputisdesired,clickOutputTypeuntiltheLVPECLoptiondisplays.Thisoption
automaticallyenablesonboardLVPECLtermination.IfLVDSoutputisdesired,useOutputTypeto
selecttheLVDSoption.
Step4.PLLBandwidthSelect.
IftheuserwantstoadjustthePLLbandwidth,clicktheLoopFilterblock,bringingapop-upscreenas
showninFigure6.
Figure6.ChronosGUI—LoopFilterConfigurationPop-Up
ForacleanreferenceinputtotheCDCE421(forexample,fromanoscillatororcrystal),themaximum
bandwidthandphasemarginsettingmustbeused:400kHzbandwidthand80degrees.ThePhase
FrequencyDetector(PFD)chargepumpcurrentmustbesettoitsmaximum,224µA.ThePFDcharge
pumpcurrentcanbesetbyclickingonthePDFChargePumpblock,presentingadrop-downmenu
withthevariouschargepumpcurrentsettings.
ForadirtyreferenceinputtotheCDCE421,theminimumbandwidthof50kHzmustbeused.
Additionally,toreducetheoutputjitterforadirtyinput,thephasemargincanalsobereducedtonear
itsminimum(30degrees),dependingontheintegrationlimitsofthejitterthatareimportantforagiven
application.Toreducetheoutputjitterfurther,thechargepumpcurrentcanbereducedtoitsminimum
(56µA),dependingontheintegrationlimitsofthejitter.
Step5.WritetoCDCE421EEPROM.
TowriteanyparticularsettingtotheEEPROM(lockingornonlocking),theDevice_EEPROM
drop-downmenu(atthetopofthescreen)mustbeselected.ThismenucontainstheitemsWrite
settingstoEEPROM(Nolocking)andWritesettingstoEEPROM(Locking).Choosetheappropriate
optionaftersettingthedesiredPLLconfigurationstowritetotheEEPROMinitsappropriatemode.
10.9MHz–1175MHzLowPhaseNoiseClockEvaluationBoard 10SCAU020–March2007
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