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2SignalPathandControlCircuitry
SignalPathandControlCircuitry
TheCDCE421canaccepta27MHz—38.33MHzfrequencyinputfromeitheranLVCMOSsource(upto
3.3V)oracrystalinthesamefrequencyrange.
TheCDCE421EVMisdividedintofourblocks.Theprogrammingsectionanddevicepowerforeachsector
canbeenabledordisabledthroughindividualswitchesprovidedforeachblock.Forexample,inorderto
enablepowerandprogrammingforBlockA,theswitchmustbeinthesettingshowninFigure2.The
otherblocksareenabledanddisabledwiththerespectiveswitchesinthesamemanner.
TheCDCE421outputfrequencyisalwaysanintegermultipleorintegerdivideoftheinputfrequency,and
isdeterminedthroughselectionofVCO1orVCO2andtheappropriateprescalarandoutputdivider,based
ontheCDCE421datasheet.
Theloopfilterselectionaffectstheoutputfrequencyphasenoiseandshouldbeconsideredinconjunction
withthetypeofinputused.
InLVDSmode,thedevicecanachieveupto500MHzoutput.InLVPECLmode,thedevicecanachieve
1175MHzoutput.TheoutputsignalinglevelandLVPECLterminationareselectablethroughthesoftware
interface.
Figure2.CDCE421EVMProgrammingBlocks
10.9MHz–1175MHzLowPhaseNoiseClockEvaluationBoard 6SCAU020–March2007
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