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Glossary
A-6
indirect addressing: An addressing mode in which an address points to
another pointer rather than to the actual data; this mode is prohibited in
RISC architecture.
instruction fetch packet: A group of up to eight instructions held in memory
for execution by the CPU.
internal interrupt: A hardware interrupt caused by an on-chip peripheral.
internal peripherals: Devices connected to and controlled by a host device.
The C6x internal peripherals include the direct memory access (DMA)
controller, multichannel buffered serial ports (McBSPs), host port inter-
face (HPI), external memory-interface (EMIF), and runtime support tim-
ers.
interrupt: A signal sent by hardware or software to a processor requesting
attention. An interrupt tells the processor to suspend its current opera-
tion, save the current task status, and perform a particular set of instruc-
tions. Interrupts communicate with the operating system and prioritize
tasks to be performed.
interrupt service fetch packet (ISFP): A fetch packet used to service inter-
rupts. If eight instructions are insufficient, the user must branch out of this
block for additional interrupt service. If the delay slots of the branch do
not reside within the ISFP, execution continues from execute packets in
the next fetch packet (the next ISFP).
interrupt service routine (ISR): A module of code that is executed in re-
sponse to a hardware or software interrupt.
interrupt service table (IST) A table containing a corresponding entry for
each of the 16 physical interrupts. Each entry is a single-fetch packet and
has a label associated with it.
IRQ: Interrupt request; see IRQ module.
IRQ module: IRQ is an API module that manages CPU interrupts.
IST: See interrupt service table.
L
least significant bit (LSB): The lowest-order bit in a word.
LED: The LED API Module.
linker: A software tool that combines object files to form an object module,
which can be loaded into memory and executed.