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TMP92CZ26A
92CZ26A-434
Stage change condition of control write transfer type
1. Receive SETUP token from host.
• Start setup stage in UDC.
• Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.
• Change data stage in UDC.
2. Receive OUT token from host.
• CPU receive request from request register every INT_SETUP
interrupt.
• Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.
• Receive dataphase data normally, and set EP0 bit of DATASET
register.
• CPU receives data in FIFO by setting DATASET.
• CPU process receiving data by device request.
• When CPU finish transaction, it writes “0” to EP0 bit of EOP register.
• Change status stage in UDC.
3. Receive IN token from host.
• Return data packet of 0 data to IN token, and state change to IDLE in
UDC.
• Assert INT_STATUS interrupt to external when receive ACK for 0
data packet.
These changing conditions are shown in
Figure 3.16.11.
Figure 3.16.11 The Control Flow in UDC (Control Write Transfer Type)
In control read transfer type, transaction number of data stage do not always
accord with data number that is apppointed by device request. Therefore, CPU
can be processd by using INT_STATUSNAK interrupt. However, when class and
vendor request is used, be accord wLength value with data transfer number in
data phase. By this setting, using this interrupt is not need. Data stage data can
be confirmed by accessing DATASIZE register.
SETUP DATA0 ACK IN NAK
DATA0
DATA1DATA1
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType registe
r
bRequest register
wValue register
wIndex register
wLength register
Setup Received registe
r
EP0_FIFO (RD of payload)
EP0_FIFO (Rest data) EOP registe
r
OUT ACK IN ACKOUT ACK DATA0OUT NAK