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TX9956XBG-533/600
Superscalar Architecture
TX99 Processor Core Features
The TX99 Family of RISC microprocessors is based on the MIPS64
TM
microarchitecture of MIPS Technologies, Inc.
(U.S.A.) These microprocessors have a 64-bit superscalar architecture developed jointly by MIPS and Toshiba.
MIPS64
TM
has the highest performance in the industry, enabling simultaneous execution of two instructions. By using
this architecture in semiconductors and systems, it is possible to achieve high-speed data processing in fields such
as automotive (digital information), OA, home servers, digital information appliances and networks where cost and
power consumption are the top priority.
TX99 Family
64-Bit Superscalar TX System RISC
Can be used as a CPU core for custom SoC
Under
development
Based on MIPS 25Kf high-end RISC core
Instruction set: MIPS 64
TM
with MIPS-3D
TM
ASE
Employs dual issue superscalar pipeline (7-stage)
Core operation frequency: 533 MHz/600 MHz
Equipped with 32-Kbyte instruction cache and
32-Kbyte data cache
employs 4-way set-associative system
Level 2 cache of up to 256 Kbytes can be installed
(optional)
Built-in single/double precision floating point coprocessor
SOC I/F with a high bus band width (12.8 Gbytes/s)
with numerous bus frequency division ratios for core
vs. SOC I/F
TX99/H4: 90-nm process technology
Complete development environment
64-bit RISC microprocessor using a Superscalar architecture
● 64-bit Superscaler equipped with
TX99/H4 core
● On-chip caching
Four-way set-associative caches
Instruction cache: 32 Kbytes
Data cache: 32 Kbytes
Level 2 cache: 256 Kbytes
● External bus (SysAD bus)
64-/32-bit
● Single-/double-precision FPU
● Clock generator (CG)
● Low power consumption mode
● Built-in debug support unit (DSU)
● Maximum operating frequency:
Core: 533 MHz/600 MHz
External bus: 133 MHz
● I/O operating voltage: 2.5 V or 3.3 V
Internal operating voltage: 1.25 V
● Package:
272-pin PBGA, 27 mm x 27 mm,
1.27-mm pitch (with 16 thermal balls)
The TX9956XBG is equipped with a TX99/H4 core that uses a 90 nm
process to enable 533 or 600 MHz operation. This processor has a
built-in floating-point unit (FPU) and SysAD bus interface, and is useful
in a wide range of applications areas including LBPs and set-top
boxes. It contains 32-Kbyte instruction cache and 32-Kbyte data cache,
as well as large secondary cache of 256 Kbytes.
TX99/H4 Core
Integer Arithmetic
Unit
256-Kbyte Level 2 Cache
System Control
Coprocessor
Coprocessor
Registers
Memory Management Unit
48 Double-Entry TLB
Exception Handling Unit
Floating-Point
Unit
Coprocessor
Floating-Point
Unit
Registers
Floating-Point
Unit Data
Path Logic
32-KB 4-Way
Set-Associative
Instruction Cache
64-Bit
General-
Purpose
Registers
Dual
Issue
Pipeline
Control
Integer
Arithmetic
Data Path
Logic
MAC Unit
32-KB 4-Way
Set-Associative
Data Cache
Cache Controller
Write
buffer
Clock
Generator
Debug
Support Unit
(EJTAG)
SysAD
Bus
Interface
MGB II Bus
MGB II Bus
SysAD Bus Interface