Toshiba TLCS-900 Family Personal Computer User Manual


 
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TMPR4938XBG-300/333
Built-in PCI controllers, Ether MAC
64-bit RISC microprocessor with built-in PCI controller and Ether MAC
TMPR4955CFG-400 TMPR4956CXBG-400
Achieves 400 MHz operation
The TMPR4938XBG is a 64-bit RISC microprocessor ideal for net-
works and digital consumer applications. It is based on the TX49/H3
core and has a variety of built-in functions, including PCI controller,
Ether MAC, DMA controller, NAND Flash controller, memory control-
ler, UART and timers. The processor runs at 33/66 MHz, and the PCI
bus at 300/333 MHz.
64-bit RISC equipped with TX49/H3 core
On-chip caching
Four-way set-associative caches
Instruction cache: 32 Kbytes built in
Data cache: 32 Kbytes built in
Cache lock function
Memory management unit (TLB): 64 entries
4 K / 16 K / 64 K / 256 K / 1 M / 4 Mbyte pages
Memory controller: SDRAM (64-bit, 133 MHz)
Supports NAND Flash, SRAM, ROM,
NOR Flash and I/O
Interrupt controller: 6 external sources
32-bit timer: 3 channels
UART: 2 channels
PCI controller (32-bit, 33/66 MHz)
DMA controller: 8 channels
AC-Link (AC97 interface)
Ether MAC: 2 channels
I/O ports: 16-bit
Maximum operating frequency: 300/333 MHz
I/O supply voltage: 3.3 V
Internal supply voltage: 1.5 V
Package: 484-pin PBGA
(with 64-pin thermal balls)
TX49/H3 core
Debug Support Unit (DSU)
Data Cache
(32K)
Instruction
Cache (32K)
IU
MMU
BIU
Write
Buffer
Floating-Point Unit (FPU)
G BUS Interface
General
Purpose
Register
MAC unit
64-bit
G-BUS
Clock Generator
NAND Flash Controller
SDRAM Controller
External Bus Interface
DMA Controller
PCI Controller
Ether MAC
IM BUS Bridge
AC-Link
UART Timer Parallel I/O
Interrupt
Controller
64-bit RISC microprocessors that can easily be enhanced with desired functions
The TMPR4955CFG and TMPR4956CXBG are equipped with a
TX49/H4 core that uses a 90-nm process to enable 400 MHz opera-
tion. These processors have a built-in floating point unit (FPU) and
SysAD bus interface, and are useful in a wide range of application
areas including LBP, networks and set-top boxes. A debug support
unit (DSU) is also built in, and this enables real-time PC tracing and
various types of execution control.
64-bit RISC equipped with TX49/H4 core
Five-stage pipeline
On-chip caching
4-way set-associative caches
Instruction cache: 32 Kbytes built in
Data cache: 32 Kbytes built in
Cache lock function
48 double-entry TLB
External bus (SysAD bus):
32-bit (TMPR4955CFG)
64-/32-bit (TMPR4956CXBG)
Single-/double-precision FPU
Low power consumption mode
Built-in debug support unit (DSU)
Maximum operating frequency:
Core: 400 MHz
External bus: 133 MHz
I/O supply voltage: 2.5 V or 3.3 V
Internal supply voltage: 1.25 V
Package:
160-pin QFP (TMPR4955CFG)
217-pin PFBGA (TMPR4956CXBG)
TX49/H4 Core
Integer Arithmetic
Unit
System Control
Processor
Coprocessor
Registers
Memory Management
Unit (MMU)
48 Double-Entry TLB
Exception
Handling Unit
Floating-Point Unit
Coprocessor
Floating-Point
Unit Registers
Floating-Point
Unit Data Path
Logic
64-Bit
General-
Purpose
Registers
Pipeline
Control
Integer
Arithmetic
Data Path
Logic
MAC
Unit
Clock
Generator
Sync Circuit
Debug
Support Unit
(EJTAG)
32-KB 4-Way
Set-Associative
Instruction Cache
32-KB 4-Way
Set-Associative
Data Cache
Cache
Controller
Write
Buffer
32-Bit
SysAD Bus
Interface