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TX19
Family
32
-bit
TX System RISC
Quick interrupt response
Conventional RISC processor
TX19 TX19A
Software processing
Use of hardware for
part of interrupt processing
Displays outstanding efficiency in control programs heavy with bit operations.
Automated interrupt processing
reduces burden on software.
Save SFRs on stack
Read entry address
Jump to entry address
Enable interrupts
Decide interrupt level
Set CPU registers
Jump to vector address
Save general-purpose registers on stack
Hardware processing
Software processing
Save SFRs on stack
Read entry address
Jump to entry address
Enable interrupts
Decide interrupt level
Set CPU registers
Jump to vector address
Save general-purpose registers on stack
Hardware processing
Software processing
Save SFRs on stack
Read entry address
Jump to entry address
Enable interrupts
Decide interrupt level
Set CPU registers
Jump to vector address
Save general-purpose registers on stack
10 20 %
(compared to conventional
Toshiba RISC CPU core)
Code size
Code efficiency of the
highest level in RISC
Architecture
New instructions are added to enable bit manipulation,
format conversion, and saving/restoring multiple registers.
Addition of CP0 instructions allows all processing to be
performed with only MIPS16e-TX.
Shadow registers
Compiler
The compiler tailored to TX19A is provided.
The TX19A core features the MIPS16e-TX architecture that realizes enhanced code efficiency and performance.
Excellent code efficiency
MIPS16e-TX
TX19
MIPS16
TX19A
MIPS16e-TX
MIPS16e
TM
16-/32-bit
Toshiba-defined
extended instructions
16-/32-bit