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17/27 XM-7002B Rev.1.0
6.2.4.Timing of Host Interface (Ultra DMA )
Figure 12 shows the Host Interface Ultra DMA word Timings
DMARQ
DMACK-
STOP
DMARDY
STROBE
DD
(15:0)
tMLI
tUI
tACK
tFS
tENV
t2AD
t2IORDY
t2CYC
tRP
tRFS
tLI
tACK
tDVS tDVH
CRC
tDVHtDVS
tDVH
tDVS
tDVHtDVS
tCYC
tCYC
Ultra DMA Mode 2
timing parameters min (ns) max (ns)
Min time (ns) Max time (ns)
t2CYC
Typical Sustained Average Cycle time
120
tCYC
Cycle time
55
tDVS
Data Setup time
34
tDVH
Data Hold time
6
tUI
Unlimited Interlock time
0
tACK
Setup and Hold Time for DMACK-
20
tENV
Envelope time
20 70
t2AD
Minimum Delay time for Driver
0
t2IORODY
Minimum time for DMACK-
20
tFS
First STROBE time
0 170
tRFS
Ready-to-Final STROBE time
50
tRP
Ready-to-Pause time
100
tLI
Limited Iuterlock time
0 150
tMLI
Interlock with minimum
20
Figure 12 Host Interface Timing (Ultra DMA)