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Initial Program Load (IPL): a feature built into BBS-compliant devices, describing those devices as
capable of loading and executing an OS, as well as being able to provide control back to the BIOS if the
loading attempt fails.
IPL: see Initial Program Load.
IRQ (Interrupt Request): an electronic request that runs from a hardware device to the CPU. The interrupt
controller assigns priorities to incoming requests and delivers them to the CPU. It is important that there is
only one device hooked up to each IRQ line; doubling up devices on IRQ lines can lock up your system.
Plug-n-Play operating systems can take care of these details for you.
ISA (I
ndustry Standard Architecture): a slower 8- or 16-bit bus (data pathway).
Latency: the amount of time that one part of a system spends waiting for another part to catch up. This is
most common when the system sends data out to a peripheral device, and it waiting for the peripheral to
send some data back (peripherals tend to be slower than onboard system components).
Mirroring: see RAID.
NVRAM: ROM and EEPROM are both examples of Non-Volatile RAM, memory that holds its data without
power. DRAM, in contrast, is volatile.
OEMs (O
riginal Equipment Manufacturers): Compaq or IBM package other companies’ motherboards
and hardware inside their case and sell them.
Parallel port: transmits the bits of a byte on eight different wires at the same time (that is, in parallel form,
eight bits at the same time).
PCI (P
eripheral Component Interconnect): a 32 or 64-bit local bus (data pathway) which is faster than the
ISA bus. Local buses are those which operate within a single system (as opposed to a network bus, which
connects multiple systems).
PCI PIO (PCI P
rogrammable Input/Output) modes: the data transfer modes used by IDE drives. These
modes use the CPU for data transfer (in contrast, DMA channels do not). PCI refers to the type of bus
used by these modes to communicate with the CPU.
PCI-to-PCI bridge: allows you to connect multiple PCI devices onto one PCI slot.
Pipeline burst SRAM: a fast secondary cache. It is used as a secondary cache because SRAM is slower
than SDRAM, but usually larger. Data is cached first to the faster primary cache, and then, when the pri-
mary cache is full, to the slower secondary cache.