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Phoenix – AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
Current FSB Frequency
Current DRAM Frequency
DRAM Clock
DRAM Timing
DRAM CAS Latency
Bank Interleave
Precharge to Active (Trp)
Tras Non-DDR400/DDR400
Active to CMD (Trcd)
DRAM Command Rate
DRAM Burst Len
Write Recovery Time
[133MHz]
[166MHz]
[By SPD]
[Auto By SPD]
[2.5]
[Disabled]
[4T]
[7T/10T]
[5T]
[2T Command]
[4]
[2T]
Item Help
_________________________
Menu Level ►
↑↓←→: Move
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Current FSB Frequency:
Show current FSB frequency
Current DRAM Frequency:
Show current DRAM frequency
DRAM Clock:
Select setting for DRAM clock
By SPD / 133 MHZ / 166 MHZ / 200 MHZ
DRAM Timing :
Select setting for SDRAM timing
Manual / AUTO By SPD / Turbo / Ultra
DRAM CAS Latency:
This setting defines the number of cycles after a read command until output starts.
1.5/ 2 / 2.5 / 3
Bank Interleave:
Select Bank Interleave
Disabled / 2 Bank / 4 Bank
Precharge to Active (Trp):
This item controls the number of DRAM clocks used for DRAM Trp parameters.
2T / 3T / 4T / 5T
Tras Non-DDR400/DDR400: