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POST code checkpoints
The POST code checkpoints are the largest set of checkpoints
during the BIOS pre-boot process. The following table describes
the type of checkpoints that may occur during the POST portion
of the BIOS
.
Checkpoint Code Description
03 Disable NMI, Parity, video for EGA, and DMA control-
lers. Initialize BIOS, POST, and Runtime data area.
Also initialize BIOS modules on POST entry and GPNV
area.
Initialized CMOS as mentioned in the Kernel Variable
"wCMOSFlags."
04 Check CMOS diagnostic byte to determine if battery
power is OK and CMOS checksum is OK. Verify CMOS
checksum manually by reading storage area.
If the CMOS checksum is bad, update CMOS with
power-on default values and clear passwords. Initial-
ize status register A.
Initializes data variables that are based on CMOS
setup questions.
Initializes both the 8259 compatible PICs in the sys-
tem.
05 Initializes the interrupt controlling hardware (gener-
ally PIC) and interrupt vector table.
06 Do R/W test to CH-2 count reg. Initialize CH-0 as sys-
tem timer. Install the POSTINT1Ch handler. Enable
IRQ-0 in PIC for system timer interrupt. Traps INT1Ch
vector to "POSTINT1ChHandlerBlock."
08 Initializes the CPU. The BAT test is being done on
KBC.
Program the keyboard controller command byte is
being done after Auto detection of KB/MS using AMI
KB-5.
C0 Early CPU Init Start -- Disable Cache - Init Local APIC.
C1 Set up boot strap processor Information.
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