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User Manual version 2305
APOLLO 120/150 III
7-122
u CONCURRENT FUNCTION (MEM)
This item is CPU & PCI Masters Concurrently Access Memory
Function. Select enabled allows CPU access memory cycles
and PCI masters access memory cycles concurrently issued
onto host bus and PCI bus, respectively, and then the
memory access cycles will be rearranged by SiS630 to
memory sequentially.
The choice: Enabled or Disabled.
u CONCURRENT FUNCTION (PCI)
This item is CPU & PCI Masters Concurrently Access PCI Bus
Function. Select enabled allows CPU access PCI bus cycle and
PCI masters access memory cycles concurrently issued onto
host bus and PCI bus, respectively.
The choice: Enabled or Disabled.
u CPU PIPELINE CONTROL
When enabled this item, only one pending cycle is allowed at
one time.
When disabled, there might be more than two pending cycles
at one time depends on the CPU behavior.
The choice: Enabled or Disabled.
u PCI DELAY TRANSACTION
If the chipset has an embedded 32-bit write buffer to support
delay transaction cycles, you can enable this item to provide
compliance with PCI Ver.2.1 specifications. We recommend
that you leave this item at the default value.
The choice: Enabled or Disabled.
u MEMORY PARITY CHECK
Enabled this item to test the boot-up memory. .
The choice: Enabled or Disabled.