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ASUS P2E-M User’s Manual 47
IV. BIOS SOFTWARE
IV. BIOS
Chipset Features
Video Memory Cache Mode (UC)
USWC (uncacheable, speculative write combining) is a new cache technology for
the video memory of the processor. It can greatly improve the display speed by
caching the display data. You must leave this on the default setting of UC
(uncacheable) if your display card cannot support this feature or else your system
may not boot.
PCI 2.1 Support (Enabled)
This function allows you to Enable or Disable PCI 2.1 features. Leave on Enabled
setting for PCI 2.1 compliancy.
Memory Hole At 15M–16M (Disabled)
Enabling this feature reserves 15MB to 16MB memory address space to ISA expan-
sion cards that specifically require this setting. This makes the memory from 15MB
and up unavailable to the system. Expansion cards can only access memory up to
16MB. The default is Disabled.
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Onboard FDC Controller (Enabled)
When Enabled, this field allows you to connect your floppy disk drives to the onboard
floppy disk drive connector instead of a separate controller card. If you want to use a
different controller card to connect the floppy disk drives, set this field to Disabled.
Onboard FDC Swap A & B (No Swap)
This field allows you to reverse the hardware drive letter assignments of your floppy
disk drives. Two options are available: No Swap and Swap AB. If you want to switch
drive letter assignments through the onboard chipset, set this field to Swap AB.
Onboard Serial Port 1 (3F8H/IRQ4)
Settings are 3F8H/IRQ4, 2F8H/IRQ3, 3E8H/IRQ4, 2E8H/IRQ10, and Disabled for
the onboard serial connector.
Onboard Serial Port 2 (2F8H/IRQ3)
Settings are 3F8H/IRQ4, 2F8H/IRQ3, 3E8H/IRQ4, 2E8H/IRQ10, and Disabled for
the onboard serial connector.
Onboard Parallel Port (378H/IRQ7)
This field sets the address of the onboard parallel port connector. You can select
either: 3BCH / IRQ 7, 378H / IRQ 7, 278H / IRQ 5, Disabled. If you install an I/O card
with a parallel port, ensure that there is no conflict in the address assignments. The PC
can support up to three parallel ports as long as there are no conflicts for each port.