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Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
3-3
3.2.1 PENTIUM MMX MICROPROCESSOR
The Pentium MMX microprocessor is software-compatible with earlier generation x86
microprocessors but provides significantly higher performance due to both higher processing
speed and enhanced design (Figure 3-2.).
Figure 3–2.
Pentium MMX Microprocessor Internal Architecture
The Pentium MMX microprocessor contains a dual-ALU CPU, branch prediction logic, dual-
pipeline math coprocessor, and a 32-KB cache that is split into two 16-KB 4-way, set-associative
caches for handling code and data separately. The microprocessor is mounted in a ZIF type 7
socket for easy changing/upgrading of the microprocessor. Replacing the microprocessor may
require reconfiguring the settings of DIP switch SW1 to properly set the speed of the Host bus
and the core (processing) frequencies.
3.2.1.1 MMX Technology
The CPU of the Pentium MMX supports 57 additional instructions specifically designed for
accelerating multimedia and communications applications. Such applications often involve
compute-intensive loops that can take up as much as 90 percent of CPU execution time. The
MMX logic, using a parallel processing technique called Single Instruction-Multiple Data
(SIMD), operates on 64 bits at a time. The MMX instructions are designed to take advantage of
the dual-pipeline CPU as well as help the programmer in avoiding branches in code. Specific
applications that benefit from MMX technology include 2D/3D graphics, audio, speech
recognition, video codecs, and data compression .
NOTE:
MMX operations utilize a portion of the floating point registers of the
integrated math coprocessor. Programmers should take note that mixing MMX code
with that of floating point operations can result in reduced performance and should
therefore be avoided.
.
Pentium MMX Microprocessor
CPU
w/MMX
Branch
Prediction
Dual Pipeline
Math Coproc.
32-KB
Cache