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CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B Page 6 of 37
Selection Guide
CY7C0430CV
–133
CY7C0430CV
–100 Unit
f
MAX2
133
[1]
100 MHz
Max Access Time (Clock to Data) 4.2 5.0 ns
Max Operating Current I
CC
750 600 mA
Max Standby Current for I
SB1
(All ports TTL Level) 200 150 mA
Max Standby Current for I
SB3
(All ports CMOS Level) 15 15 mA
Pin Definitions
Port 1 Port 2 Port 3 Port 4 Description
A
0P1
–A
15P1
A
0P2
–A
15P2
A
0P3
–A
15P3
A
0P4
–A
15P4
Address Input/Output.
I/O
0P1
–I/O
17P1
I/O
0P2
–I/O
17P2
I/O
0P3
–I/O
17P3
I/O
0P4
–I/O
17P4
Data Bus Input/Output.
CLK
P1
CLK
P2
CLK
P3
CLK
P4
Clock Input. This input can be free running or strobed.
Maximum clock input rate is f
MAX
.
LB
P1
LB
P2
LB
P3
LB
P4
Lower Byte Select Input. Asserting this signal LOW
enables read and write operations to the lower byte. For
read operations both the LB and OE signals must be
asserted to drive output data on the lower byte of the data
pins.
UB
P1
UB
P2
UB
P3
UB
P4
Upper Byte Select Input. Same function as LB, but to the
upper byte.
CE
0P1
,CE
1P1
CE
0P2
,CE
1P2
CE
0P3
,CE
1P3
CE
0P4
,CE
1P4
Chip Enable Input. To select any port, both CE
0
AND
CE
1
must be asserted to their active states (CE
0
≤ V
IL
and
CE
1
≥ V
IH
).
OE
P1
OE
P2
OE
P3
OE
P4
Output Enable Input. This signal must be asserted LOW
to enable the I/O data lines during read operations. OE
is
asynchronous input.
R/W
P1
R/W
P2
R/W
P3
R/W
P4
Read/Write Enable Input. This signal is asserted LOW
to write to the dual port memory array. For read opera-
tions, assert this pin HIGH.
MRST Master Reset Input. This is one signal for All Ports.
MRST
is an asynchronous input. Asserting MRST LOW
performs all of the reset functions as described in the text.
A MRST
operation is required at power-up.
CNTRST
P1
CNTRST
P2
CNTRST
P3
CNTRST
P4
Counter Reset Input. Asserting this signal LOW resets
the burst address counter of its respective port to zero.
CNTRST
is second to MRST in priority with respect to
counter and mask register operations.
MKLD
P1
MKLD
P2
MKLD
P3
MKLD
P4
Mask Register Load Input. Asserting this signal LOW
loads the mask register with the external address
available on the address lines. MKLD
operation has
higher priority over CNTLD
operation.
CNTLD
P1
CNTLD
P2
CNTLD
P3
CNTLD
P4
Counter Load Input. Asserting this signal LOW loads the
burst counter with the external address present on the
address pins.
CNTINC
P1
CNTINC
P2
CNTINC
P3
CNTINC
P4
Counter Increment Input. Asserting this signal LOW
increments the burst address counter of its respective port
on each rising edge of CLK.
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