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CY7C1353G
Document #: 38-05515 Rev. *E Page 13 of 13
Document History Page
Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05515
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 224363 See ECN RKF New data sheet
*A 288431 See ECN VBL Deleted 66 MHz
Changed TQFP package in Ordering Information section to Pb-free TQFP
*B 333626 See ECN SYT Removed 117-MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP Packages
according to JEDEC standards and updated the Pin Definitions accordingly
Modified V
OL,
V
OH
test conditions
Replaced ‘Snooze’ with ‘Sleep’
Replaced TBD’s for Θ
JA
and Θ
JC
to their respective values on the Thermal
Resistance table
Updated the Ordering Information by shading and unshading MPNs
according to availability
*C 418633 See ECN RXU Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from V
IH
< V
DD
to
V
IH
< V
DD
Modified test condition from V
DDQ
< V
DD
to V
DDQ
< V
DD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D 480124 See ECN VKN Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND.
Updated the Ordering Information table.
*E 1274724 See ECN VKN/AESA Corrected typo in the Ordering Information table
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