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CY7C63413C
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Document #: 38-08027 Rev. *B Page 27 of 32
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Figure 8. Clock Timing
CLOCK
t
CYC
t
CL
t
CH
Figure 9. USB Data Signal Timing
Figure 10. Receiver Jitter Tolerance
90%
10%
90%
10%
D−
D+
t
r
t
f
V
crs
V
oh
V
ol
Differential
Data Lines
Paired
Transitions
N * T
PERIOD
+ T
JR2
T
PERIOD
Consecutive
Transitions
N * T
PERIOD
+ T
JR1
T
JR
T
JR1
T
JR2
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