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CY7C68000A
Document #: 38-08052 Rev. *G Page 7 of 15
24 B8 Tri_state Input Tri-state Mode Enable Places the CY7C68000A into Tri-state mode
which tri-states all outputs and IOs. Tri-state Mode can only be enabled
while suspended.
0: Disables Tri-state Mode
1: Enables Tri-state Mode
19 C2 LineState1 Output Line State These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then
they are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
18 C1 LineState0 Output Line State These signals reflect the current state of the single-ended
receivers. They are combinatorial until a ‘usable’ CLK is available then
they are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
00–0: SE0
01–1: ‘J’ State
10–2: ‘K’ State
11–3: SE1
15 B6 OpMode1 Input Operational Mode These signals select among various operational
modes.
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved
14 B5 OpMode0 Input Operational Mode These signals select among various operational
modes.
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved
54 A5 TXValid Input Transmit Valid This signal indicates that the data bus is valid. The asser-
tion of Transmit Valid initiates SYNC on the USB. The negation of Trans-
mit Valid initiates EOP on the USB. The start of SYNC must be initiated
on the USB no less than one or no more that two CLKs after the assertion
of TXValid.
In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the
USB between 8- and 16-bit times after the assertion of TXValid is detected
by the Transmit State Machine.
In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less
than one or more than two CLKs after the assertion of TXValid is detected
by the Transmit State Machine.
1 A8 TXReady Output Transmit Data Ready If TXValid is asserted, the SIE must always have
data available for clocking in to the TX Holding Register on the rising edge
of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge
of CLK, the CY7C68000A loads the data on the data bus into the TX
Holding Register on the next rising edge of CLK. At that time, the SIE
should immediately present the data for the next transfer on the data bus
.
Table 1. Pin Descriptions (continued)
QFN VFBGA Name Type Default Description
[1]
(continued)
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