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CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I Page 44 of 56
Figure 22. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
T
SUSTOI2C
Setup Time for STOP Condition 4.0 –0.6– μs
T
BUFI2C
Bus Free Time Between a STOP and START
Condition
4.7 –1.3– μs
T
SPI2C
Pulse Width of spikes are suppressed by the
input filter.
– –050ns
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
SU;DAT
Š 250 ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specifica-
tion) before the SCL line is released.
Table 49. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 – –kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0 – – – μs
T
LOWI2C
LOW Period of the SCL Clock 4.7 – – – μs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 – – – μs
T
SUSTAI2C
Setup Time for a Repeated START Condition 4.7 – – – μs
T
HDDATI2C
Data Hold Time 0 – – – μs
T
SUDATI2C
Data Setup Time 250 – – –ns
T
SUSTOI2C
Setup Time for STOP Condition 4.0 – – – μs
T
BUFI2C
Bus Free Time Between a STOP and START
Condition
4.7 – – – μs
T
SPI2C
Pulse Width of spikes are suppressed by the
input filter
– – – –ns
Table 48. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd > 3.0V (continued)
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
SDA
SCL
S
Sr SP
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
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