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CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *I Page 45 of 56
Packaging Information
This section illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 23. 8-Pin (300-Mil) PDIP
0.115
0.100 BSC.
0.125
0.055
0.014
0.015 MIN.
0.145
0.070
0.022
0.140
SEATING
PLANE
0.380
0.240
0.180 MAX.
0.300
0.430 MAX.
0.325
0.008
0°-10°
0.015
0.390
0.260
DIMENSIONS IN INCHES MIN.
MAX.
PIN 1 ID
14
58
51-85075 *A
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