Cypress CYD01S36V Computer Hardware User Manual


 
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G Page 20 of 28
Figure 14. Counter Reset
[43, 44]
Notes
43.CE
0
= BE0 – BE3 = LOW; CE
1
= MRST = CNT/MSK = HIGH.
44.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
45.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value
Switching Waveforms (continued)
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATA
IN
ADDRESS
CNTRST
R/W
DATA
OUT
A
n
A
m
A
p
A
x
0
1
A
n
A
m
A
p
Q
1
Q
n
Q
0
D
0
t
CH2
t
CL2
t
CYC2
t
SA
t
HA
t
SW
t
HW
t
SRST
t
HRST
t
SD
t
HD
t
CD2
t
CD2
t
CKLZ
[45]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS A
n
ADDRESS A
m
READ
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