Filter
Top Products
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G Page 21 of 28
Figure 15. Readback State of Address Counter or Mask Register
[46, 47, 48, 49]
Notes
46.CE
0
= OE = BE0 – BE3 = LOW; CE
1
= R/W = CNTRST = MRST = HIGH.
47.Address in output mode. Host must not be driving address bus after t
CKLZ
in next clock cycle.
48.Address in input mode. Host can drive address bus after t
CKHZ
.
49.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK
level) being Read out on the address lines.
Switching Waveforms (continued)
CNTEN
CLK
t
CH2
t
CL2
t
CYC2
ADDRESS
ADS
A
n
Q
x-2
Q
x-1
Q
n
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
LOAD
ADDRESS
EXTERNAL
t
CD2
INTERNAL
ADDRESS
A
n+1
A
n+2
A
n
t
CKHZ
DATA
OUT
A
n*
Q
n+3
Q
n+1
Q
n+2
A
n+3
A
n+4
t
CKLZ
t
CA2
or t
CM2
READBACK
INTERNAL
COUNTER
ADDRESS
INCREMENT
EXTERNAL
A
0
–A
16
[+] Feedback