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Award BIOS SETUP 3-8
• DRAM RAS Only Refresh: Permits queuing up to four DRAM refresh
requests, so DRAM can refresh at optimal times. The default value is Dis-
abled.
Enabled: The DRAM Refresh type is RAS only.
Disabled: The DRAM Refresh type is CAS before RAS.
• ECC Checking/Generation: The default value is Enabled.
ECC: This field is enabled the optional DRAM Error Checking and
Correction (ECC) with 72-bit Wide memory.
Parity: This field is enabled the optional DRAM parity Error with 72-bits
wide memroy
Disabled: Disabled the ECC parity function.
• Fast DRAM Refresh: The cache DRAM controller offers two refresh
modes, Normal and Hidden. In both modes, CAS takes place before RAS
but the Normal mode requires a CPU cycle for each. On the other hand, a
cycle is eliminated by “hiding” the CAS refresh in Hidden mode. Not only is
the Hidden mode faster and more efficient, but it also allows the CPU to
maintain the status of the cache even if the system goes into a power manage-
ment “suspend” mode.
Enabled: Hidden Mode
Disabled: Normal Mode
• Read-Around-Write: DRAM optimization feature (Default is Enabled)
Enabled: If a memory read is addressed to a location whose latest write is
being held in a buffer before being written to memory, the read is
satisfied through the buffer contents, and the read is not sent to the
DRAM.
Disabled: Memory read is addressed to a location on whose write through to
memory.
• PCI Burst Write Combine:
Enabled: Chipset assembles long PCI bursts from the data held in these
buffers.
Disabled: The chipset doesn’t assemble long PCI bursts from the data held in
these buffers
• PCI-To-DRAM Pipeline: DRAM optimization feature:
Enabled: full PCI-to-DRAM write pipelining is enabled. Buffers in the
chipset store data written from the PCI bus to memory.
Disabled: When Disabled, PCI writes to DRAM are limited to a single
transfer per write cycle.