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5-16
Event Status and Event Status Enable Registers
The Event Status Register (ESR) assigns specified events to specific bits (see Figure 5-4
and Table 5-6). When a bit in the ESR is set (i.e., 1), the event that corresponds to that bit
has occurred since the register was last read or cleared. For example, if bit 3 (DDE) is set
to 1, a device-dependent error has occurred.
The Event Status Enable Register (ESE) is a mask register that allows the host to enable
or disable (mask) each bit in the ESR. When a bit in the ESE is 1, the corresponding bit
in the ESR is enabled. When any enabled bit in the ESR changes from O to 1, the ESB bit
in the Status Byte Register also goes to 1. When the ESR is read (using the *ESR? com-
mand) or cleared (using the *CLS command), the ESB bit in the Status Byte Register
returns to 0.
0
1
2
345
6
7
0
1
2
345
6
7
&
&
&
&
&
&
&
&
Logical OR
Standard
Event Status Register
*ESR?
Standard
Event Status Enable
Register
*ESE *ESE?
Power On
User Request
Command Error
Execution Error
Device Dependent Error
Query Error
Request Control
Operation Complete
Summary Message
Event Summary Bit (ESB)
(Bit 5 of Status Byte Register)
aam22f.eps
Figure 5-4. Event Status and Event Status Enable Registers
Figure 5-4 reprinted from ANSI/IEEE Std 488.2-1987. Copyright 1988. By the Institute of Electrical and Electronics Engineers, Inc. By
permission of the IEEE Standards Department
.