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PC Specialist's Handbook ErgoPro m664-series
Edition 1 - Release 1 - March 1998 Page 5-5
BIOS check points (POST codes)
At the beginning of each POST task, the BIOS outputs the check point (error code) to I/ O port 80h. If the BIOS
detects a terminal error condition, it issues a terminal-error beep code (See BEEP CODES earlier in this
section), attempts to display the check point on upper left corner of the screen and on the port 80h LED display,
and halts POST. It attempts repeatedly to write the check point to the screen. This attempt may "hash" some
CGA displays. If the system hangs before the BIOS can process the error, the value displayed at the port 80h is
the last test performed. In this case, the screen does not display the check point.
This list shows the check point number (hex) and what BIOS is doing in POST while this checkpoint is
displayed.
Code Description of POST Operation
02h Verify real mode
03h Disable non-maskable interrupt (NMI)
04h Get processor type
06h Initialize system hardware
08h Initialize chipset with initial POST values
09h Set IN POST flag
0Ah Initialize CPU registers
0Bh Enable CPU cache
0Ch Initialize caches to initial POST values
0Eh Initialize I/O component
0Fh Initialize the local bus IDE
10h Initialize power management
11h Load alternate registers with initial POST valuesnew
12h Restore CPU control word during warm boot
13h Initialize PCI bus mastering devices
14h Initialize keyboard controller
16h BIOS ROM checksum
17h Initialize cache before memory autosize
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset programmable interrupt controller
20h Test DRAM refresh
22h Test keyboard controller
24h Set ES segment register to 4 GB
26h Enable A20 line
28h Autosize DRAM
29h Initialize POST memory manager
2Ah Clear 512 KB base RAM
2Ch RAM failure on address line xxxx*
2Eh RAM failure on data bits xxxx* of low byte of memory bus
2Fh Enable cache before system BIOS shadow