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RCV56HCF PCI/CardBus Modem Designer’s Guide
ROCKWELL PROPRIETARY INFORMATION
1129
3-22
3.3 INTERFACE TIMING AND WAVEFORMS
3.3.1 PCI Bus Timing
The PCI interface timing conforms to the PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995.
3.3.2 Serial EEPROM Timing
The serial EEPROM interface timing is listed in Table 3-11 and is shown in Figure 3-6.
Table 3-11. Timing - Serial EEPROM Interface
Symbol Parameter Min Typ. Max Units Test Condition
t
CSS
Chip select setup 400 500 – ns
t
CSH
Chip select hold 400 500 – ns
t
DOS
Data output setup 400 500 – ns
t
DOH
Data output hold 400 500 – ns
t
PD0
Data input delay – – 400 ns
t
PD1
Data input delay – – 400 ns
t
DF
Data input disable time – – 100 ns
t
SV
Status valid – – 100 ns
t
SKH
Clock high 500 – – ns
t
SKL
Clock low 500 – – ns
1123F3-7 EEPROM
SROMCS (CS)
SROMIN (DO) (PROGRAM)
SROMOUT (DI)
SROMIN (DO) (READ)
SROMCLK (SK)
t
CSS
t
SKL
t
SKH
t
DOH
t
DOS
t
CSH
t
PD1
t
DF
t
DF
t
PD0
t
SV
Figure 3-6. Waveforms - Serial EEPROM Interface