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34
2 System Board
Chip-Set
and slave controllers are connected.
Counter / Timer The chip contains a three-channel 82C54 counter/timer. The counters use a
division of the 14.318 MHz OSC input as the clock source.
Serial EEPROM This is the non-volatile memory which holds the values for the Setup
program (they are no longer stored in the CMOS memory). The Serial
EEPROM is described on page 43
.
Cache Memory
There are two integrated circuits sealed within a single Pentium II package.
One of these contains the Level-2 (L2) cache memory chip; the other
contains the processor, which itself includes two banks of Level-1 (L1)
cache memory.
The L1 cache memory has a total capacity of 32KB (16 KB data, 16 KB
instruction). The L2 cache memory has a capacity 512 KB, and is composed
of four-way set-associative static RAM. Data is stored in lines of 32-bytes
(256 bits). Thus two consecutive 128-bit transfers with the main memory
are involved for each transaction.
The amount of cache memory is set by Intel at the time of manufacture, so
cannot be changed.