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Specification Clarifications
16 Intel
®
80303 and 80302 I/O Processors Specification Update
6. SREQ64# Functionality
Problem: There is an SREQ64# functionality difference between the A-1 and A-2 steppings of the 80303 I/O
processors. (This functionality is also on the 80302 since it is based on the A-2 stepping.) During
the power up sequence, the S_REQ64# signal is sampled by PCI devices on the secondary PCI bus
to determine 64-bit or 32-bit PCI operation. On the A-1 stepping, S_REQ64# is deasserted one
P_CLK after the deassertion of S_RST# (as stated in the Developer's Manual and Datasheet). On
the A-2 stepping, SREQ64# is deasserted approximately 600ps after the deassertion of S_RST#.
The PCI Local Bus Specification, Revision 2.2 has a setup and hold specification for REQ64# with
respect to RST#. Even though the Intel Datasheets and Developer's Manuals state that,
“S_REQ64# is deasserted one P_CLK after the deassertion of S_RST#”, the PCI Local Bus
Specification, Revision 2.2 states that the RST# to REQ64# hold time is 0-50ns. Since the RST# to
REQ64# hold time can be zero, compliant devices should be sampling REQ64# during the
REQ64# to RST# setup time which is a minimum of 10 clock cycles. (see pages 128 and 135,
table 4-6 and figure 4-11 of the PCI Local Bus Specification, Revision 2.2)
The implication of this change is that some 64-bit PCI devices on the secondary PCI bus only
works in 32-bit PCI mode. This could be due to using a non-PCI compliant device or because of
trace delays between the S_RST# and S_REQ64# signals. Verify proper functionality on 80303
A-2 designs. The processor stepping identification is listed page 10. Also see Documentation
Changes #32 and 33 for corrections to the datasheet and manual.
7. PCI Local Bus Specification, Revision 2.3 Compliancy
Problem: The Intel
®
80303 I/O processor (80303) was designed to be compliant with the PCI Local Bus
Specification, Revision 2.2. (This functionality is also on the 80302 since it is based on the A-2
stepping.). Since the release of the 80303, the PCI Special Interest Group has released a new
specification revision, PCI Local Bus Specification, Revision 2.3. There are no plans to step the
80303 to make it compliant with the PCI Local Bus Specification, Revision 2.3.
8. DMA and AAU End of Chain Functionality
Problem: There is a case where a race condition occurs between the End of Chain (EOC), Channel Active
(CA) and resume bit, which causes a bogus EOC. The Intel
®
80303 I/O processor (80303) (this
functionality is also on the 80302 since it is based on the A-2 stepping.) asserts the EOC bit when
the NDAR is zero, even when the chain resume bit is set. When the resume bit is set, the CA bit is
cleared for one cycle and then set again, modifying the CA and EOC at the same time.
Consider the case when a chain has been added to the list after the last descriptor is read by the
DMA. In this case, the resume bit gets set by software. The EOC occurs because the NDAR was
zero when read and the CA bit is momentarily cleared. The DMA processes the resume and sets the
CA bit again. It remains active until it again reaches an NDAR of 0.
One way to handle this condition, is for the software to track the last descriptor believed to be in
memory. To compare the NDAR and DAR in the DMA descriptor MMR space, to see when they
are 0, and are the last expected DAR. In this situation, the DMA is already idle and the CA bit is
clear. When not, ignore the EOC interrupt. A bogus EOC is detected when NDAR is not 0 and
resume is set.