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36 Intel
®
80303 and 80302 I/O Processors Specification Update
24. Table 8-15 on page 8-36 needs clarification
Problem: ICON.10, Global Interrupt Enable bit, does not state what bit value enables interrupts.
Workaround: Add this sentence to the bit description, 'A '0' will globally enable interrupts, and a '1' globally
disables interrupts.'
Affected Docs: Intel
®
80303 I/O Processor Developer’s Manual
25. Table 13-13 on page 13-30 has incorrect data
Problem: Syndrome Decoding Error Types and Symptoms are incorrectly stated.
Workaround: Replace Table 13-13 with the following and, add the adjacent paragraph with “new” Figure 13-16:
Figure 13-16 shows how the data flows through the ECC hardware for a read transaction.
Affected Docs: Intel
®
80303 I/O Processor Developer’s Manual
Table 13-13. Syndrome Decoding
Error Type Symptom
None The syndrome is 0000 0000.
Single-Bit Use the H-Matrix in Figure 13-17 to determine which bit the MCU will invert to fix the error.
Multi-Bit If the Syndrome does not match an 8-bit value in the H-matrix, the error is uncorrectable
Figure 13-16. ECC Read Data Flow
A8160-01
Main
Memory
MCU
ECC
Memory
64-bit Bus
Address and Control Bus
8-bit Bus
64-bit Bus
Error Type/Location
Calculate ECC
with G-matrix
H-matrix
Look-up Table
Data to Internal Bus
Data Corrector
(single-bit error)
Calculate Syndrome by
Comparing ECC w/Check Bits