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8086
Table 1 Pin Description (Continued)
Symbol Pin No Type Name and Function
QS
1
QS
0
24 25 O QUEUE STATUS The queue status is valid during the CLK cycle after
which the queue operation is performed
QS
1
and QS
0
provide status to allow external tracking of the internal
8086 instruction queue
QS
1
QS
0
Characteristics
0 (LOW) 0 No Operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent Byte from Queue
The following pin function descriptions are for the 8086 in minimum mode (ie MNMX
e
V
CC
) Only the pin
functions which are unique to minimum mode are described all other pin functions are as described above
MIO 28 O STATUS LINE logically equivalent to S
2
in the maximum mode It is used to
distinguish a memory access from an IO access MIO
becomes valid in
the T
4
preceding a bus cycle and remains valid until the final T
4
of the cycle
(M
e
HIGH IO
e
LOW) MIO floats to 3-state OFF in local bus ‘‘hold
acknowledge’’
WR 29 O WRITE indicates that the processor is performing a write memory or write
IO cycle depending on the state of the MIO
signal WR is active for T
2
T
3
and T
W
of any write cycle It is active LOW and floats to 3-state OFF in
local bus ‘‘hold acknowledge’’
INTA 24 O INTA is used as a read strobe for interrupt acknowledge cycles It is active
LOW during T
2
T
3
and T
W
of each interrupt acknowledge cycle
ALE 25 O ADDRESS LATCH ENABLE provided by the processor to latch the
address into the 82828283 address latch It is a HIGH pulse active during
T
1
of any bus cycle Note that ALE is never floated
DTR 27 O DATA TRANSMITRECEIVE needed in minimum system that desires to
use an 82868287 data bus transceiver It is used to control the direction of
data flow through the transceiver Logically DTR
is equivalent to S
1
in the
maximum mode and its timing is the same as for MIO
(T
e
HIGH R
e
LOW) This signal floats to 3-state OFF in local bus ‘‘hold acknowledge’’
DEN 26 O DATA ENABLE provided as an output enable for the 82868287 in a
minimum system which uses the transceiver DEN is active LOW during
each memory and IO access and for INTA cycles For a read or INTA
cycle
it is active from the middle of T
2
until the middle of T
4
while for a write cycle
it is active from the beginning of T
2
until the middle of T
4
DEN floats to 3-
state OFF in local bus ‘‘hold acknowledge’’
HOLD 31 30 IO HOLD indicates that another master is requesting a local bus ‘‘hold’’ To be
acknowledged HOLD must be active HIGH The processor receiving the
HLDA
‘‘hold’’ request will issue HLDA (HIGH) as an acknowledgement in the
middle of a T
4
or T
i
clock cycle Simultaneous with the issuance of HLDA
the processor will float the local bus and control lines After HOLD is
detected as being LOW the processor will LOWer the HLDA and when the
processor needs to run another cycle it will again drive the local bus and
control lines Hold acknowledge (HLDA) and HOLD have internal pull-up
resistors
The same rules as for RQ
GT apply regarding when the local bus will be
released
HOLD is not an asynchronous input External synchronization should be
provided if the system cannot otherwise guarantee the setup time
5