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Software Developer’s Manual 167
Ethernet Interface
STATUS.ASDV [9:8], provides the results of speed status indication for diagnostics purposes
regardless of whether the Auto-Speed Detection feature is enabled. This function is initiated with a
write to the CTRL_EXT.ASDCHK bit. See Section 13.4.6 for details.
8.6.2.2.3 Automatic Detection of Link Speed using SPD-IND
With the CTRL register configure as CTRL.FRCSPD = 0, the speed is reconfigured automatically
each time a new linkup event is detected. This configuration is recommended why the PHY is
configured for Auto-Negotiation.
8.6.2.3 Duplex
The duplex configuration of the link is also resolved during the Auto-Negotiation process. As
previously mentioned, the Ethernet controller supports both full- and half-duplex operation in
internal PHY mode. When the PHY asserts its link signal to the MAC, it also communicates the
duplex setting.
Software can override the duplex setting via the CTRL.FD bit when the CTRL.FRCDPLX (force
duplex) bit is set. If CTRL.FRCDPLX is 0b, the CTRL.FD bit is ignored.
8.6.2.4 MII Management Registers
The software driver is required under some circumstances to read from, or write to, the MII
management registers in the PHY. These accesses are performed via the MDIC registers. The MII
registers allow the software driver to have direct control over the PHY’s operation, which includes:
• Resetting the PHY
• Setting preferred link configuration for advertisement during the Auto-Negotiation process
• Restarting the Auto-Negotiation process
• Reading Auto-Negotiation status from the PHY
• Forcing the PHY to a specific link configuration
• Extended capabilities
The standard set of PHY management registers can be found in the IEEE P802.3ab standard.
8.6.2.5 Comments Regarding Forcing Link
Forcing link in GMII/MII mode requires the software driver to configure both the MAC and the
PHY in a consistent manner with respect to each other as well as the link partner. After
initialization, the software driver configures the desired modes in the MAC, then accesses the PHY
MII registers to set the PHY to the same configuration.
In internal PHY mode, setting the CTRL.SLU bit forces a link up condition in the MAC. The
duplex setting at this point should be forced by software on the CTRL.FD bit.